The Stellaris family of microcontrollers are the first ARM® Cortex-M3 based microcontrollers, and feature :

• Up to 80 MHz operation with 32-bit ARM Cortex-M3 architecture,
• 8K to 256K Single-cycle Flash,
• 8K to 64K Single-cycle SRAM,
• Flexible Timer Capability,
• Up to 4 general purpose timer,
• 24-bit system (SysTick) timer,
• 32-bit watchdog timer,
• Several serial interfaces,
• LDO voltage regulator.

When using Stellaris family, user should be aware of the following :

• Locking pins,
• Start-up,
• and Advanced Peripheral Bus and Advanced High-Performance Bus.

Locking pins

All MCUs, except x00 family, provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]).
Therefore these pins need to be unlocked before their function can be changed. Refer to GPIO Library for GPIO handling routines.

Caution : It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller.
If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches.

As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger.
Or, if possible, by simply adding few seconds delay at the beginning of your code.

Start-up

Upon reset, MCU will execute Start-up sequence in order to configure the oscillator block.
Start-up sequence will configure Reset and Clock Control registers (RCC and RCC2) using the settings given in the Edit Project window.

Advanced Peripheral Bus and Advanced High-Performance Bus

Advanced Peripheral Bus (APB) interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface; the APB has unpipelined protocol.
All signal transitions are only related to the rising edge of the clock to enable the integration of APB peripherals easily into any design flow. Every transfer takes at least two cycles.

APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals and is optimized for minimal power consumption and reduced interface complexity.
APB bus has an address and data phase similar to AHB, but a much reduced low complexity signal list, for example no bursts.

The Advanced High-Performance (AHB) is a new level of bus which sits above the APB and implements the features required for high-performance, including:

• burst transfers,
• split transactions,
• single cycle bus master handover,
• single clock edge operation,
• non-tristate implementation,
• wider data bus configurations (64/128 bits).

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