PIC32 Memory Organization
The PIC32MX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program memory, data memory, SFRs and Configuration registers reside in this address space at their respective unique addresses.
The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing the PIC32MX to execute from data memory.
Key features of PIC32MX memory organization include the following :
- 32-bit native data width
- Separate User and Kernel mode address spaces.
- Flexible program Flash memory partitioning.
- Flexible data RAM partitioning for data and program space.
- Separate boot Flash memory for protected code.
- Robust bus-exception handling to intercept runaway code.
- Simple memory mapping with Fixed Mapping Translation (FMT) unit.
- Cacheable and non-cacheable address regions.
PIC32MX Memory Layout
The PIC32MX microcontrollers implement two address spaces: virtual and physical.
All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Peripherals, such as DMA and Flash controllers, use physical addresses and access memory independently of the CPU.
Virtual addresses are exclusively used by the CPU to fetch and execute instructions. Virtual address space can be thought as CPU’s logical view and use of its physical resources.
A graphical representation of the PIC32MX virtual and physical memory is shown in picture below :
PIC32 Memory Map
As it can be seem, the entire 4 GB virtual address space is divided into two primary regions: User and Kernel space. The lower 2 GB of space called USEG/KUSEG, and the upper 2 GB are divided into KSEG0, KSEG1, KSEG2 and KSEG3.
Virtual vs Physical Addresses
The PIC32MX’s CPU uses virtual addresses to address the peripherals, which means that to access the PIC32MX’s peripherals we (and the CPU) must be operating within the virtual boundaries of KSEG1.
The PIC32MX’s CPU also uses virtual addressing to fetch and execute program memory instructions.
If you look closely, you’ll see that the physical address region between the INTERNAL RAM (at physical address 0x00000000) and the INTERNAL BOOT FLASH (beginning at physical address 0x1FC00000)
is matched up with the virtual memory schemes of KSEG0 and KSEG1.
The PIC32MX CPU maps the virtual areas of KSEG0 and KSEG1 against the same physical memory area beginning at physical address 0x00000000.
Because both the KSEG0 and KSEG1 virtual segments point to the same physical memory area, the PIC32MX CPU can execute instructions from either the KSEG0 or KSEG1 virtual memory segment, depending on the cacheable status of the application (KSEG0 and USEG-KSEG are cacheable while KSEG1 is not cacheable).
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