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STM32 Family Specifics

This topic discusses basic STM32 family specifics.

• STM32 F4 Specifics
• STM32 F2 Specifics
• STM32 F1 Specifics
• Start-up
• Advanced Peripheral Bus and Advanced High-Performance Bus

STM32 F4 Specifics

The STM32 F4-series is the first group of STM32 microcontrollers based on the ARM Cortex-M4F core.
The main features for this series are :

• ARM Cortex-M4F core at a maximum clock rate of 168 MHz.
• The Flash memory has the following main features :
  • Capacity up to 1 Mbyte
  • 128 bits wide data read
  • Byte, half-word, word and double word write
  • Sector and mass erase
• Prefetch instruction and cache memory,
• Embedded SRAM feature 4 Kbytes of backup plus 192 Kbytes of system SRAM. The system SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
• Oscillators consists of internal (16 MHz, 32 kHz), optional external (4 to 26 MHz, 32.768 to 1000 kHz).
• Common peripherals included are :
  • USB 2.0 OTG HS and FS,
  • Two CAN 2.0B,
  • One SPI + two SPI or full-duplex I2S,
  • Three I2C,
  • Four USART,
  • Two UART,
  • SDIO for SD/MMC cards,
  • Twelve 16-bit timers,
  • Two 32-bit timers,
  • Two watchdog timers,
  • Temperature sensor,
  • 16 or 24 channels into three ADCs,
  • Two DACs,
  • 51 to 140 GPIOs,
  • Improved real-time clock (RTC),
  • Cyclic redundancy check (CRC) engine,
  • Random number generator (RNG) engine.
• The STM32F4x7 models add ethernet MAC and camera interface.
• The STM32F41x models add a cryptographic processor for DES / TDES / AES, and a hash processor for SHA-1 and MD5.

STM32 F2 Specifics

The STM32 F4-series are the STM32 microcontrollers based on the ARM Cortex-M3 core.
The main features for this series are :

• ARM Cortex-M4F core at a maximum clock rate of 120 MHz.
• The Flash memory has the following main features :
  • Capacity up to 1 Mbyte
  • 128 bits wide data read
  • Byte, half-word, word and double word write
  • Sector and mass erase
• Prefetch instruction and cache memory,
• Embedded SRAM feature 4 Kbytes of backup plus 192 Kbytes of system SRAM. The system SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
• Oscillators consists of internal (16 MHz, 32 kHz), optional external (4 to 26 MHz, 32.768 to 1000 kHz).
• Common peripherals included are :
  • USB 2.0 OTG HS,
  • Two CAN 2.0B,
  • One SPI + two SPI or I2S,
  • Three I2C,
  • Four USART,
  • Two UART,
  • SDIO for SD/MMC cards,
  • Twelve 16-bit timers,
  • Two 32-bit timers,
  • Two watchdog timers,
  • Temperature sensor,
  • 16 or 24 channels into three ADCs,
  • Two DACs,
  • 51 to 140 GPIOs,
  • Improved real-time clock (RTC),
  • Cyclic redundancy check (CRC) engine,
  • Random number generator (RNG) engine.
• The STM32F2x7 models add ethernet MAC and camera interface.
• The STM32F21x models add a cryptographic processor for DES / TDES / AES, and a hash processor for SHA-1 and MD5.

STM32 F1 Specifics

The STM32 F1-series are the group of STM32 microcontrollers based on the ARM Cortex-M3 core.
The main features for this series are :

• ARM Cortex-M3 core at a clock rate up to 72 MHz.
• The Flash memory for XL-density devices has density of up to 1 Mbyte, for other devices density of up to 512 Kbytes.
  The Flash memory can be programmed 16 bits (half words) at a time.
• Embedded SRAM feature up to 96 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits).
• Oscillators consists of internal (16 MHz, 32 kHz), optional external (4 to 26 MHz, 32.768 to 1000 kHz).
• Common peripherals included are :
  • USB 2.0 OTG HS,
  • One CAN 2.0B,
  • Up to three SPI,
  • Up to two I2C,
  • Up to five USART,
  • Two UART,
  • SDIO for SD/MMC cards,
  • Up to fourteen 16-bit timers,
  • Two 24-bit timers,
  • Two watchdog timers,
  • Up to 21 ADC channels,
  • Two 12-bit DACs,
  • Real-time clock (RTC).
• The STM32F2x7 models add ethernet MAC and camera interface.
• The STM32F21x models add a cryptographic processor for DES / TDES / AES, and a hash processor for SHA-1 and MD5.

Start-up

Upon reset, MCU will execute Start-up sequence in order to configure the oscillator block.
Start-up sequence will configure Reset and Clock Control registers (RCC and RCC2) using the settings given in the Edit Project window.

Advanced Peripheral Bus and Advanced High-Performance Bus

Advanced Peripheral Bus (APB) interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface; the APB has unpipelined protocol.
All signal transitions are only related to the rising edge of the clock to enable the integration of APB peripherals easily into any design flow. Every transfer takes at least two cycles.

APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals and is optimized for minimal power consumption and reduced interface complexity.
APB bus has an address and data phase similar to AHB, but a much reduced low complexity signal list, for example no bursts.

The Advanced High-Performance (AHB) is a new level of bus which sits above the APB and implements the features required for high-performance, including:

• burst transfers,
• split transactions,
• single cycle bus master handover,
• single clock edge operation,
• non-tristate implementation,
• wider data bus configurations (64/128 bits).