ARM Memory Organization

The Cortex-M3 and Cortex-M4 have a predefined memory map. This allows the built-in peripherals, such as the interrupt controller and the debug components, to be accessed by simple memory access instructions.
Thus, most system features are accessible in program code. The predefined memory map also allows the Cortex-M3 processor to be highly optimized for speed and ease of integration in system-on-a-chip (SoC) designs.

Overall, the 4 GB memory space can be divided into ranges as shown in picture below. The Cortex-M3 design has an internal bus infrastructure optimized for this memory usage.

A graphical representation of the ARM memory is shown in picture below :

ARM Memory Map

ARM Memory Map

The ARM Cortex-M3 memory is divided into following regions :

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